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MK68901 december 1988 multiCfunction peripheral . 8 input/output pins ? individually programmable direction ? individual interrupt source capability - programmable edge selection . 16 source interrupt controller ? 8 internal sources ? 8 external sources ? individual source enable ? individual source masking ? programmable interrupt service modes - polling - vector generation - optional in-service status ? daisy chaining capability . four timers with individually pro- grammable prescaling ? two multimode timers - delay mode - pulse width measurement mode - event counter mode ? two delay mode timers ? independent clock input ? time out output option . single channel usart ? full duplex ? asynchronous to 65 kbps ? byte synchronous to 1 mbps ? internal/external baud rate generation ? dma handshake signals ? modem control ? loop back mode . 68000 bus compatible . 48 pin dip or 52 pin plcc figure 1 : pin connections. description the MK68901 mfp (multi-function peripheral) is a combination of many of the necessary peripheral functions in a microprocessor system. included are : eight parallel i/o lines interrrupt controller for 16 sources four timers single channel full duplex usart the use of the mfp in a system can significantly re- duce chip count, thereby reducing system cost. the mfp is completely 68000 bus compatible, and 24 di- rectly addressable internal registers provide the ne- mfp 1 dpip48 plcc52 1/33
necessary control and status interface to the pro- grammer. the mfp is a derivative of the mk3801 sti, a z80 family peripheral. pin description gnd : ground v cc :+5 volts ( 5%) cs : chip select (input, active, low). cs is u- sed to select the MK68901 mfp for ac- cesses to the internal registers. cs and iack must not be asserted at the same time. ds : data strobe (input, active low). ds is u- sed as part of the chip select and interrupt acknowledge functions. r/ w : read/write (input). r/ w is the signal from the bus master indicating whether the current bus cycle is a read (high) or write (low) cycle. dtack : data transfer acknowledge. (output, ac- tive low, tri-stateable) dtack is used to signal the bus master that data is ready, or that data has been accepted by the MK68901 mfp. a1-a5 : address bus (inputs). the adress bus is used to adress one of the internal regis- ters during a read or write cycle. d0-d7 : data bus (bi-directional, tri-stateable). the data bus is used to receive data from or transmit data to one of the internal re- gisters during a read or write cycle. it is also used to pass a vector during an in- terrupt acknowledge cycle. clk : clock (input). this input is used to pro- vide the internal timing for the MK68901 mfp. reset : device reset. (input, active low). reset disables the usart receiver and trans- mitter, stops all timers and forces the ti- mer outputs low, disables all interrupt channels and clears any pending inter- rupts. the general purpose interrupt/i/o lines will be placed in the tri-state input mode. all internal registers (except the ti- mer, usart data registers, and transmit status register) will be cleared. intr : interrupt request (output, active low, o- pen drain). intr is asserted when the MK68901 mfp is requesting an interrupt. intr is negated during an interrupt ac- knowledge cycle or by clearing the pen- ding interrupt(s) through software. iack : interrupt acknowledge (input, active low). iack is used to signal the MK68901 mfp that the cpu is acknowledging an interrupt. cs and iack must not be as- serted at the same time. iei : interrupt enable in (input, active low). iei is used to signal the MK68901 mfp that no higher priority device is requesting in- terrupt service. ieo : interrupt enable out (output, active low). ieo is used to signal lower priority peri- pherals that neither the MK68901 mfp nor another higher priority peripheral is requesting interrupt service. 10-17 : general purpose interrupt i/o lines. these lines may be used as interrupt in- puts and/or i/o lines. when used as in- terrupt inputs, their active edge is pro- grammable. a data direction register is u- sed to define which lines are to be hi-z inputs and which lines are to be push-pull ttl compatible outputs. so : serial output. this is the output of the u- sart transmitter. si : serial input. this is the input to the u- sart receiver. rc : receiver clock. this input controls the serial bit rate of the usart receiver. tc : transmitter clock. this input controls the serial bit rate of the usart transmitter. rr : receiver ready. (output, active low) dma output for receiver, which reflects the status of buffer full in port number 15. tr : transmitter ready. (output, active low) dma output for transmitter, which re- flects the status of buffer empty in port number 16. tao,tbo, tco,tdo: timer outputs. each of the four timers has an output which can produce a square wave. the output will change states each timer cycle ; thus one full pe- riod of the timer out signal is equal to two timer cycles. tao or tbo can be reset (logic "o") by a write to tacr, or tbcr respectively. xtal1, xtal2 : timer clock inputs. a crystal can be connected between xtal1 and xtal2, or xtal1 can be driven with a ttl level clock. when driving xtal1 with a ttl le- MK68901 2/33
vel clock, xtal2 must be allowed to float. when using a crystal, external capacitors are required. see figure 33. all chip ac- cesses are independent of the timer clock. tai,tbi : timer a, b inputs. used when running the timers in the event count or the pulse width measurement mode. the interrupt channels associated with 14 and 13 are used for tai and tbi, respectively. thus, when running a timer in the pulse width v000351 MK68901 3/33
figure 4 : register map. address port n . abbreviation register name 0 1 2 gpip aer ddr general purpose i/o active edge register data direction register 3 4 5 6 7 8 9 a b iera ierb ipra iprb isra isrb imra imrb vr interrupt enable register a interrupt enable register b interrupt pending register a interrupt pending register b interrupt in-service register a interrupt in-service register b interrupt mask register a interrupt mask register b vector register c d e f 10 11 12 tacr tbcr tcdcr tadr tbdr tcdr tddr timer a control register timer b control register timers c and d control register timer a data register timer b data register timer c data register timer d data register 13 14 15 16 17 scr ucr rsr tsr udr sync character register usart control register receiver status register transmitter status register usart data register interrupts the general purpose i/o-interrupt port (gpip) pro- vides eight i/o lines that may be operated either as inputs or outputs under software control. in addition, each line may generate an interrupt in either a po- sitive going edge or a negative going edge of the in- put signal. the gpip has three associated registers. one al- lows the programmer to specify the active edge for each bit that will trigger an interrupt. another register specifies the data direction (input or output) asso- ciated with each bit. the third register is the actual data i/o register used to input or output data to the port. these three registers are illstrated in figure 5. the active edge register (aer) allows each of the general purpose interrupts to provide an interrupt on either a 1-0 transition or a 0-1 transition. writing a zero to the appropriate bit of the aer causes the associated input to produce an interrupt on the 1-0 transition. the edge bit is simply one input to an ex- clusive-or gate, with the other input coming from the input buffer ant the output going to a 1-0 transition detector. thus, depending upon the state of the in- put, writing the aer can cause an interrupt-produ- cing transition, which will cause an interrupt on the associated channel, if that channel is enabled. one would then normally configure the aer before enabling interrupts via iera and ierb. note : changing the edge bit, with the interrupt enabled, may cause an interrupt on that channel. the data direction register (ddr) is used to define 10-17 as inputs or as outputs on a bit by bit basis. writing a zero into a bit of the ddr causes the cor- responding interrupt-i/o pin to be a hi-z input. wri- ting a one into a bit of the ddr causes the cor- responding pin to be configured as a push-pull out- put. when data is written into the gpip, those pins defined as inputs will remain in the hi-z state while those pins defined as outputs will assume the state (high or low) of their corresponding bit in the gpip. when the gpip is read, the data read will come di- rectly from the corresponding bit of the gpip register for all pins defined as output, while the data read on all pins defined as inputs will come from the input buffers. each individual function in the MK68901 is provided with a unique interrupt vector that is presented to the system during the interrupt acknowledge cycle. the interrupt vector returned during the interrupt ac- knowledge cycle is shown in figure 6, while the vec- tor register is shown in figure 7. MK68901 4/33
there are 16 vector addresses generated internally by the MK68901, one for each of the 16 interrupt channels. the interrupt control registers (figure 8) provide control of interrupt processing for all i/o facilities of the MK68901. these registers allow the program- mer to enable or disable any or all of the 16 inter- rupts, providing masking for any interrupt, and pro- vide access to the pending and in-service status of the interrupt. optional end-of-interrupt modes are available under software control. all the interrupts are prioritized as shown in figure 9. figure 5 : general purpose i/o registers. figure 6 : interrupt vector. v000352 v000353 MK68901 5/33
figure 7 : vector register. figure 8 : interrupt control registers. v000354 v000355 MK68901 6/33
figure 9 : interrupt control register definitions priority channel description highest lowest 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 general purpose interrupt 7(i7) general purpose interrupt 6(i6) timer a receive buffer full receive error transmit buffer empty transmit error timer b general purpose interrupt 5(i5) general purpose interrupt 4(i4) timer c timer d general purpose interrupt 3(i3) general purpose interrupt 2(i2) general purpose interrupt 1(i1) general purpose interrupt 0(i0) interrupts may be either polled or vectored. each channel may be individual enabled or disabled by writing a one or a zero in the appropriate bit of inter- rupt enable registers (iera, ierb - see figure 8 for all registers in this section). when disabled, an in- terrupt channel is completely inactive. any internal or external action which would normally produce an interrupt on that channel is ignored and any pending interrupt on that channel will be cleared by disabling that channel. disabling an interrupt channel has no effect on the corresponding bit in interrupt in-ser- vice registers (isra, isrb) ; thus, if the in-service registers are used and an interrupt is in service on that channel when the channel is disabled, it will re- main in service until cleared in the normal manner. iera and ierb are also readable. when an interrupt is received on an enabled chan- nel, its corresponding bit in the pending register will be set. when that channel is acknowledged it will pass its vector, and the corresponding bit in the in- terrupt pending register (ipra or irpb) will be cleared. ipra and iprb are readable ; thus by pol- ling ipra and iprb, it can be determined whether a channel has a pending interrupt. ipra and iprb are also writeable and a pending interrupt can be cleared without going through the acknowledge se- quence by writing a zero to the appropriate bit. this allows any one bit to be cleared, without altering any other bits, simply by writing all ones except for the bit position to be cleared to ipra or iprb. thus a fully polled interrupt scheme is possible. note : wri- ting a one to ipra, iprb has no effect on the inter- rupt pending register. the interrupt mask registers (imra and imrb) may be used to block a channel from making an interrupt request. writing a zero into the corresponding bit of the mask register will still allow the channel to re- ceive an interrupt and latch it into its pending bit (if that channel is enabled), but will prevent that chan- nel from making an interrupt request. if that channel is causing an interrupt request at the time the cor- responding bit in the mask register is cleared, the re- quest will cease. if no other channel is making a re- quest, intr will go inactive. if the mask bit is re-en- abled, any pending interrupt is now free to resume its request unless blocked by a higher priority re- quest for service. imra and imrb are also readable . a conceptual circuit of an interrupt channel is shown in figure 10. MK68901 7/33
figure 10 : a conceptual circuit of an interrupt channel. there are two end-of-interrupt modes : the automat- ic end-of-interrupt mode and the software end-of-in- terrupt mode. the mode is selected by writing a one or a zero to the s bit of the vector register (vr). if the s bit of the vr is a one, all channels operate in the software end-of-interrupt mode. if the s bit is a zero, all channels operate in the automatic end-of- interrupt mode, and a reset is held on all in-service bits. in the automatic end-of-interrupt mode, the pending bit is cleared when that channel passes its vector. at that point, no further history of that inter- rupt remains in the MK68901 mfp. in the software end-of-interrupt mode, the in-service bit is set and the pending bit is cleared when the channel passes its vector. with the in-service bit set, no lower priority channel is allowed to request an interrupt or to pass its vector during an acknowledge sequence ; how- ever, a lower priority channel may still receive an in- terrupt and latch it into the pending bit. a higher prio- rity channel may still request an interrupt and be ac- knowledged. the in-service bit of a particular chan- nel may be cleared by writing a zero to the corre- sponding bit in isra or isrb. typically, this will be done at the conclusion of the interrupt routine just before the return. thus no lower priority channel will be allowed to request service until the higher priority channel is complete, while channels of still higher priority will be allowed to request service. while the in-service bit is set, a second interrupt on that chan- nel may be received and latched into the pending bit, though no service request will be made in re- sponse to the second interrupt until the in-service bit is cleared. isra and isrb may be read at any time. only a zero may be written into any bit of isra and isrb ; thus the in-service bits may be cleared in soft- ware but cannot be set in software. this allows any one bit to be cleared, without altering any other bits, simply by writing all ones except for the bit position to be cleared to isra or isrb, as with ipra and iprb. figure 11 a : a conceptual circuit of the MK68901 mfp daisy chaining. v000356 v000357 MK68901 8/33
figure 11 b : daisy chaining. each interrupt channel responds with a discrete 8- bit vector when acknowledged. the upper four bits of the vector are set by writing the upper four bits of the vr. the four low order bits (bit 3-bit 0) are ge- nerated by the interrupting channel. to acknowledge an interrupt, iack goes low, the iei input must go low (or be tied low) and the MK68901 mfp must have an acknowledgeable interrupt pen- ding. the daisy chaining capability (figure 11) re- quires that all parts in a chain have a common iack. when the common iack goes low, all parts freeze and prioritize interrupts in parallel. then priority is passed down the chain, via iei and ieo, until a part which has a pending interrupt is reached. the part with the pending interrupt, passes a vector, does not propagate ieo, and generates dtack. figure 9 describes the 16 prioritized interrupt chan- nels. as chown, general purpose interrupt 7 has the highest priority, while general purpose interrupt 0 is assigned the lowest priority. each of these channels may be reprioritized, in effect, by selectively ma- sking interrupts under software control. the binary numbers under "channel" correspond to the modi- fied bits iv3, iv2, iv1 and iv0, respectively, of the interrupt vector for each channel (see figure 6). each channel has an enable bit contained in iera or ierb, a pending latch contained in ipra or iprb, a mask bit contained in imra or imrb, and an inC service latch contained in isra or isrb. additional- ly, the eight general purpose interrupts each have an edge bit contained in the active edge register (aer), a bit to define the line as input or output contained in the data direction register (ddr) and an i/o bit in the general purpose interrupt-i/o port (gpip). timers there are four timers on the MK68901 mfp. two of the timers (timer a and timer b) are full function ti- mers which can perform the basic delay function and can also perform event counting, pulse width measurement, and waveform generation. the other two timers (timer c and timer d) are delay timers only. one or both of these timers can be used to sup- ply the baud rate clocks for the usart. all timers are prescaler/counter timers with a common inde- pendent clock input (xtal1, xtal2). in addition, all timers have a time-out output, function that toggles each time the timer times out. the four timers are programmed via three timer control registers and four timer data registers. ti- mers a and b are controlled by the control registers tacr and tbcr, respectively (see figure 12), and by the data registers tadr and tbdr (figure 13). timers c and d are controlled by the control register tcdcr (see figure 14) and two data registers tcdr and tddr. bits in the control registers allow the selection of operational mode, prescale, and control white the data registers are used to read the timer or write into the time constant register. timer a and b input pins tai and tbi, are used for the e- vent and pulse width modes for timers a and b. with the timer stopped, no counting can occur. the timer contents will remain unaltered while the timer is stopped (unless reloaded by writing the timer da- ta register), but any residual count in the prescaler will be lost. v000358 MK68901 9/33
in the delay mode, the prescaler is always active. a count pulse will be applied to the main timer unit each time the prescribed number of timer clock cy- cles has elapsed. thus, if the prescaler is program- med to divide by ten, a count pulse will be applied to the main counter every ten cycles of the timer clock. each time a count pulse is applied to the main coun- ter, it will decrement its contents. the main counter is initially loaded by writing to the timer data regis- ter. each count pulse will cause the current count to decrement. when the timer has decremented down to "01" , the next count pulse will not cause it to de- crement to "00". instead, the next count pulse will cause the timer to be reloaded from the timer data register. additionally, a "time out" pulse will be pro- duced. this time out pulse is coupled to the timer interrupt channel, and, if that channel is enabled, an interrupt will be produced. the time out pulse is al- so coupled to the timer output pin and will cause the pin to change states. the output will remain in this new state until the next time out pulse occurs. thus the output will complete one full cycle for each two time out pulses. if, for example, the prescaler were programmed to divide by ten, and the timer data register were loa- ded with 100 (decimal), the main counter would de- crement once for every ten cycles of the timer clock. a time out pulse will occur (hence an interrupt if that channel is enabled) every 1000 cycles of the timer clock, and the timer output will complete one full cy- cle every 2000 cycles of the timer clock. the main counter is an 8-bit binary down counter. it may be read at any time by reading the timer data register. the information read is the information last clocked into the timer read register when the ds pin had last gone high prior to the current read cycle. when written, data is loaded into the timer data re- gister, and the main counter, if the timer is stopped. if the timer data register is written while the timer is running, the new word is not loaded into the timer until it counts through h"01". however, if the timer is written while it is counting through h"01", an inde- terminate value will be written into the timer constant register. this may be circumvented by ensuring that the data register is not written when the count is h"01". if the main counter is loaded with "01", a time out pulse will occur every time the prescaler presents a count pulse to the main counter. if loaded with "00", a time out pulse will occur every 256 count pulses. figure 12 : timer a and b control registers. * unused bits : read as zeros. v000359 MK68901 10/33
figure 13 : timer data registers (a, b, c, and d). figure 14 : timer c and d register. * unused bits : read as zeros. v000360 v000361 MK68901 11/33
figure 15 : a conceptual circuit of the mfp timers in the pulse width measurement mode. changing the prescale value with the timer running can cause the first time out pulse to occur at an in- determinate time, (no less than one nor more than 200 timer clock cycles times the number in the time constant register), but subsequent time out pulses will then occur at the correct interval. in addition to the delay mode described above, ti- mers a and b can also function in the pulse width measurement mode or in the event count mode. in either of these two modes, an auxiliary control signal is required. the auxiliary control input for timer a is tai, and for timer b, tbi is used. the interrupt chan- nels associated with 14 and 13 are used for tai and tbi, respectively, in pulse width mode. see figure 15. the pulse width measurement mode functions much like the delay mode. however, in this mode, the auxiliary control signal on tai or tbi acts as an enable to the timer. when the control signal on tai or tbi is inactive, the timer will be stopped. when it is active, the prescaler and main counter are allowed to run. thus the width of the active pulse on tai or tbi is determined by the number of timer counts which occur while the pulse allows the timer to run. the active state of the signal on tai or tbi is de- pendent upon the associated interrupt channel's edge bit (gpip 4 for tai and gpip 3 for tbi : see active edge register in figure 5). if the edge bit as- sociated with the tai or tbi input is a one, it will be active high ; thus the timer will be allowed to run when the input is at a high level. if the edge bit is a zero, the tai or tbi input will be active low. as pre- viously stated, the interrupt channel (13 or 14) as- sociated with the input still functions when the timer is used in the pulse width measurement mode. how- ever, if the timer is programmed for the pulse width measurement mode, the interrupt caused by tran-si- tions on the associated tai or tbi input will occur on the opposite transition. for example, if the edge bit associated with the tai input (aer-gpip 4) is as one, an interrupt would normally be generated on the 0-1 transition of the 14 input signal. if the timer associated with this input (timer a) is placed in the pulse width measurement mode, the interrupt will occur on the 1-0 tran-sition of the tai signal instead. because the edge bit (aer-gpip 4) is a one, timer a will be allowed to count while the input is high. when the tai input makes the high to low transition, timer a will stop, and it is at this point that the interrupt will occur (as- suming that the channel is enabled). this allows the interrupt to signal the cpu that the pulse being mea- sured has terminated ; thus timer a may now be read to determine the pulse width. (again note that 13 and 14 may still be used for i/o when the timer is in the pulse width measurement mode). if timer v000332 MK68901 12/33
a is reprogrammed for another mode, interrupts will again occur on the transition, as normally defined by the edge bit. note that, like changing the edge bit, placing the timer into or taking it out of the pulse width mode can produce a transition on the signal to the interrupt channel and may cause an interrupt. if measuring consecutive pulses, it is obvious that one must read the contents of the timer and then rei- nitialize the main counter by writing to the timer data register. if the timer data register is written while the pulse is going to the active state, the write operation may result in an indeterminate value being written into the main counter. if the timer is written after the pulse goes active, the timer counts from the pre- vious contents, and when it counts through h"01", the correct value is written into the timer. the pulse width then includes counts from before the timer was reloaded. in the event count mode, the prescaler is disabled. each time the control input on tai or tbi makes an active transition as defined by the associated inter- rupt channel's edge bit, a count pulse will be gene- rated, and the main counter will decrement. in all o- ther respects, the timer functions as previously des- cribed. altering the edge bit while the timer is in the event count mode can produce a count pulse. the interrupt channel associated with the input (i3 for i4 for tai) is allowed to function normally. to count transitions reliably, the input must remain in each state (1/o) for a length of time equal to four periods of the timer clock ; thus signals of a frequency up to one fourth of the timer clock can be counted. the manner in which the timer output pins toggle states has previously been described. all timer out- puts will be forced low by a device reset. the out- put associated with timers a and b will toggle on each time out pulse regardless of the mode the ti- mers are programmed to. in addition, the outputs from timers a and b can be forced low at any time by writing a "1" to the reset location in tacr and tbcr, respectively. the output will be forced to the low state during the write operation, and at the conclusion of the operation, the output will again be free to toggle each time a time out pulse occurs. this feature will allow waveform generation. during reset, the timer data registers and the main counters are not reset. also, if using the reset option on timers a or b, one must make sure to keep the other bits in the correct state so as not to affect the operation of timers a and b. usart serial communication is provided by a full-duplex double-buffered usart, which is capable of either asynchronous or synchronous operation. variable word length and start/stop bit configurations are available under software control for asynchronous operation. for synchronous operation, a sync word is provided to establish synchronization during re- ceive operations. the sync word will also be repea- tedly transmitted when no other data is available for transmission. moreover, the MK68901 allows strip- ping of all sync words received in synchronous o- peration. the handshake control lines rr (receiver ready) and tr (transmitter ready) allow dma o- peration. separate receive and transmit clocks are available, and separate receive and transmit status and data bytes allow independent operation of the transmit and receive sections. the usart is provided with three control/status registers and a data register. the usart data register form is illustrated in figure 16. the pro- grammer may specify operational parameters for the usart via the control register, as shown in fig- ure 17. status of both the receiver and transmitter sections is accessed by means of the two status re- gisters, as shown in figures 18 and 19. data written to the data register is passed to the transmitter, while reading the data register will access data re- ceived by the usart. figure 16 : usart data register. v000362 MK68901 13/33
? 16/ ? 1 : when this bit is zero, data will be clocked into and out of the receiver and transmit- ter at the frequency of their respective clocks. when this bit is loaded with a one, data will be clocked into and out of the re- ceiver and transmitter at one sixteenth the frequency of their respective clocks. additionally, when placed in the divide by sixteen mode, the receiver data transition resynchronization logic will be enabled. wl0-wl1 :word length control. these two bits set the length of the data word (exclusive of start bits, stop bits, and parity bits as fol- lows: st0-st1 : start/stop bit control (format control). these two bits set the format as follows : parity : parity enabled. when set ("1"), parity will be checked by the receiver, parity will be calculated, and a parity bit will be inserted by the transmitter. when cleared ("0") no parity check will be made and no parity bit will be inserted for transmission. for a word length of 8 the mfp calculates the parity and appends it when transmit- ting a sync character. for shorter lengths, the parity must be stored in the sync character register (scr) along with the sync character. e/o : even-odd. when set ("1"), even parity will be used if parity is enabled. when cleared ("0"), odd parity will be used if pa- rity is enabled. note that the synchronous or asynchronous format may be selected independently of a ? 1 or ? 16 clock. thus it is possible to clock data synchronously into the device but still use start and stop bits. in this mode, all normal asynchronous format features still apply. data will be shifted in after a start bit is en- countered, and a stop bit will be checked to deter- mine proper framing. if a transmit underrun condi- tion occurs, the output will be placed in a marking state, etc. it is conversely possible to clock data in asynchronously using a synchronous format. there is data transition detection logic built into the receive clock circuitry which will re-synchronize the internal shift clock on each data transition so that, with suf- ficienty frequent data transitions, start bits are not re- quired. in this mode, all other common synchronous features function normally. this re-synchronization logic is only active in ? 16 clock mode. receiver the receiver section of the usart is configured by the ucr as previously described. the status of the receiver can be determined by reading and writing to the receiver status register (rsr). the rsr is configured as follows : figure 17 : usart control register (ucr). wl1 wl0 word length 0 0 1 1 0 1 0 1 8 bits 7 bits 6 bits 5 bits st1 st0 start bits stop bits format 0 0 ?1 1 0 1 0 1 0 1 1 1 0 1 1 1 / 2 2 sync async async async v000363 MK68901 14/33
figure 18 : receiver status register (rsr). bf : buffer full. this bit is set when the inco- ming word is transferred to the receive buffer. the bit is cleared when the re- ceive buffer is read by reading the udr. this bit of the rsr is read only. oe : overrun error. this flag is set if the inco- ming word is completely received and due to be tranferred to the receive buf-fer, but the last word in the receive buf-fer has not yet been read. when this condition occurs, the word in the receive buffer is not overwritten by the new word. note that the status flags always reflect the status of the data word currently in the re- ceive buffer. as such, the oe flag is not actually set until the good word currently in the buffer has been read. the interrupt associated with this error will also not be generated unti the old word in the receive buffer has been read. oe flag is cleared by reading the receiver status register, and new data words can- not be shifted to the receive buffer until this is done. pe : parity error. this flag is set if the word re- ceived has a parity error. the flag is set when the received word is tranferred from the shift register to the receive buf- fer if the error condition exists. the flag is cleared when the next word which does not have a parity error is tranferred to the receive buffer. fe : frame error. this flag only applies to the asynchronous format. a frame error is defined as a non-zero data word which is not followed by a stop bit. like the pe flag, the fe flag is set or cleared when a word is transferred to the receive buffer. f/s : found/ search. this combination control bit and flag bit is only used with the syn- chronous format. it can be set or cleared by writing to this bit of the rsr. when this bit is cleared, the receiver is placed in the search mode. in this mode, a bit by bit comparison of the incoming data to the character in the sync character register (scr) is made. the word length counter is disabled. when a match is found, this bit will be set automatically, and the word length counter will start as sync has not been achieved. an interrupt will be gene- rated on the receive error channel when the match occurs. the word just shifted in will, or necessity, be equal to the sync character, and it will not be transferred to the receive buffer. b : break. this flag is used only when the a- synchronous format is selected. this flag will be set when an all zero data word, fol- lowed by no stop bit, is received. the flag will stay set until both a non-zero bit is re- ceived and the rsr has been read at least once since the flag was set. break indication will not occur if the receive buff- er is full. m/cip : match/character in progress. if the syn- chronous format is selected, this flag is the match flag. it will be set each time the word transferred to the receive buffer matches the sync character. it will be re- set each time the word transferred to the receive buffer does not match the sync character. if the asynchronous format is selected, this flag represents character in progress. it will be set upon a start bit detect and cleared at the end of the word. ss : sync strip enable. if this bit is set to a one, data words that match the sync character will not be loaded into the re- ceive buffer, and no buffer full signal will be generated. re : receiver enable. this control bit is used to enable or disable the receiver. if a zero is written to this bit of the rsr, the recei- ver will turn off immediately. all flags in- cluding the f/s bit will be cleared. if a one is written to this bit, normal receiver ope- ration is enabled. the receive clock has to be running before the receiver is en- abled. v000364 MK68901 15/33
there are two interrupt channels associated with the receiver. one channel is used for the normal buffer full condition, while the other channel is used whe- never an error condition occurs. only one interrupt is generated per word received, but dedicating two channels allows separate vectors : one for the nor- mal condition, and one for an error condition. if the error channel is disabled, an interrupt will be gen-e- rated via the butter full channel, whether the word received is normal or in error. those conditions which produce an interrupt via the error channel are : overrun, parity error, frame error, sync found, and break. if a received word has an error associated with it, and the error interrupt channel is enabled, an interrupt will occur on the error channel only. each time a word is transferred into the receive buf- fer, a corresponding set of flags is latched into the rsr. no flags (except cip) are allowed to change until the data word has been read from the receive buffer. reading the receive buffer allows a new data word to be transferred to the receive buffer when it is received. thus one should first read the rsr then read the receive buffer (udr) to ensure that the flags just read match the data word just read. if done in the reverse order, it is possible that subsequent to reading the data word from the receive buffer, but prior to reading the rsr, a new word may be recei- ved and transferred to the receive buffer and, with it, its associated flags latched into the rsr. thus, when the rsr is read, those flags may actually cor- respond to a different data word. it is good practice, also to read the rsr prior to a data read as, when an overrun error occurs, the receiver will not assem- ble new characters until the rsr has been read. as previously stated, when overrun occurs, the oe flag will not be set and the associated interrupt will not be generated until the receive buffer has been read. if a break occurs, and the receive buffer has not yet been read, only the b flag will be set (oe will not be set). again, this flag will not be set until the last valid word has been read from the receive buf- fer. if the break condition ends and another whole data word is received before the receive buffer is read, both the b and oe flags will be set once the receive buffer is read. if a break occurs while the oe flag is set, the b flag will also be set. a break generates an interrupt when the condition occurs and again when the condition ends. if the break condition ends before it is acknowledged by reading the rsr, the receiver error interrupt indica- ting end of break will be generated once the rsr is read. anytime the asynchronous format is selected, start bit detection is enabled. new data is not shifted into the shift register until a zero bit is detected. if a ? 16 clock is selected, along with the asynchronous for- mat, false start bit detection is also enabled. any transition has to be stable for 3 positive going edges of the receive clock to be called a valid transition. for a start bit to be good, a valid 0-1 transition must not occur for 8 positive clock transitions after the initial valid 1-0 transition. after a good start bit has been detected, valid tran- sitions in the data are checked for continously. when a valid transition is detected, the counter is forced to state zero, and no more transition checking is started until state four. at state eight, the "previous state" of the transition checking logic is clocked into the receiver. as a result of this resynchronization logic, it is pos- sible to run with asynchronous clocks without start and stop bits if there are sufficient valid transitions in the data stream. this logic also makes the unit more tolerant of clock skew for normal asynchro- nous communications than a device which employs only start bit synchronization. figure 19 : transmitter status register (tsr). v000365 MK68901 16/33
transmitter the transmitter section of the usart is configured as to format, word length, etc. by the ucr, as pre- viously described. the status of the transmitter can be determined by reading or writing the transmitter status register (tsr). the trs is configured as fol- lows : be : buffer empty. this status bit is set when the word in the transmit buffer is transfer- red to the output shift register and thus the transmit buffer may be reloaded with the next data word. the flag is cleared when the transmit buffer is reloaded. the transmit buffer is loaded by writing to the udr. ue : this bit is set when the last word has been shifted out of the transmit shift re- gister before a new word has been loa- ded into the transmit buffer. it is not ne- cessary to clear this bit before loading the udr. this bit may be cleared by either reading the tsr or by disabling the transmitter. after the setting of the ue bit, one full transmitter clock cycle is required before this bit can be cleared by a read. the ti- ming in some systems may allow a read of the tsr before the required clock cy- cle has been completed. this would re- sult in the ue bit not being cleared until the following read. to avoid this problem, a dummy read of the tsr should be per- formed at the end of he ue service rou- tine. only one underrun error may be genera- ted between loads of the udr regardless of the number of transmitter clock cycles between udr loads. at : this bit causes the receiver to be enabled at the end of the transmission of the last word in the transmitter if the transmitter has been disabled. end : end or transmission. when the transmit- ter is turned off with a character still in the output shift register, transmission will continue until that character is shifted out. once it has cleared the output regis- ter, the end bit will be set. if no character is being transmitted when the transmitter is disabled, the transmitter will stop at the next rising edge of the internal shift clock, and end will immediately be set. the end bit is cleared by re-enabling the transmitter. b : break. this control bit will cause a break to be transmitted. when a "1" is written to the b bit of the tsr, a break will be trans- mitted upon completion of the character (if any) currently being transmitted. a break will continue to be transmitted until the b bit is cleared by writing a "0" tot his bit of the tsr. at that time, normal trans- mission will resume. the b bit has no function in the synchronous format. set- ting the "b" bit to a one keeps the "be" bit from being set to a one. so, if there were a word in the buffer at the start of break, it would remain there until the end of break, at which time it would be transmit- ted (if the transmitter is still enabled). if the buffer were not full at the start of break, it could be written at any time du- ring the break. if the buffer is empty at the end of break, the underrun flag will be set (unless the transmitter is disabled). the break bit cannot be set until the transmitter has been enabled and the transmitter has had sufficient time (one clock cycle) to perform the internal reset and initialization functions. h,l : high and low. these two control bits are used to configure the transmitter output, when the transmitter is disabled, as fol- lows : h l output state 0 0 hi-z 0 1 low ("0") 1 0 high 1 1 loop-connects transmitter output to receiver input, and tc to receiver clock (rc and si are not used ; they are bypas- sed internally). in loop back mode, trans- mitter output goes high when disabled. altering these two bits after transmitter MK68901 17/33
figure 20 : sync character register. enable (xe) is set will alter the output state until end is false. these bits should be set prior to enabling the transmitter. the state of these bits determine the state of the first transmitted character af- ter the transmitter is enabled. if the high impedance mode was selected prior to the transmitter being enabled, the first bit transmitted is indeterminate. xe : transmitter enable. this control bit is u- sed to enable or disable the transmitter. when set, the transmitter is enabled. when cleared, the transmitter will be di- sabled. if disabled, any word currently in the output register will continue to be transmitted when xe is cleared, the transmitter will turn off at the end of the break character boundary, and no end of break stop bit is transmitted. the transmit clock must be running before the trans- mitter is enabled a "one" bit always pre- cedes the first word out of the transmitter after the transmitter is enabled. there is a delay between the time the transmitter enable bit is written an when the transmit- ter reset goes low ; therefore, the h & l bits should be written with the desired state prior to enabling the transmitter. like the receiver section, there are two separate in- terrupt channels associated with the transmitter. the buffer empty condition causes an interrupt via one channel, while the underrun and end condi- tions will cause an interrupt via the second channel. when underrun occurs in the synchronous format, the character in the scr will be transmitted until a new words is loaded into the transmit buffer. in the asynchronous format, a "mark" will be continuously transmitted when underrun occurs. the transmit buffer can be loaded prior to enabling the transmitter. when the transmitter is disabled, any character currently in the process of being trans- mitted will continue to conclusion, but any character in the transmit buffer will not be transmitted and will remain in the buffer. thus no buffer empty interrupt will occur nor will the be flag be ste. if the buffer were already empty, the be flag would be set and would remain set. when the transmitter is disabled with a character in the output register but with no character in the transmit buffer, an underrun error will not oc- cur when the character in progress concludes. often it is necessary to send a break for some par- ticular period. to aid in timing a break transmission, a transmission, a transmit error interrupt will be ge- nerated at every normal character boundary time during a break transmission. the status register in- formation is unaffected by this error condition inter- rupt. it should be noted that an underrun error, if pre- sent, must be cleared from the tsr, and the inter- rupt pending register must be cleared of pending transmitter errors at the beginning of the break transmission or no interrupts will be generated at the character boundary time. it the synchronous format is selected, the sync char- acter should be loaded into the sync character re- gister (scr) as shouwn in figure 20. this character is compared to the received serial data during a search, and will be continuously transmitted during an underrun condition. all flags in the rsr or tsr will continue to function as described whether their associated interrupt channel is disabled or enabled. all interrupt chan- nels are edge triggered and, in many cases, it is the actual output of a flag bit or flag bits which is coupled to the interrupt channel. thus, if a normal interrupt producing condition occurs while the interrupt chan- nel is disabled, no interrupt would be produced even if the channel was subsequently enabled, because a transition did not occur while the interrupt channel was enabled. that particular flag bit would have to occur a second time before another "edge" was pro- duced, causing an interrupt to be generated. error conditions in the usart are determined by monitoring the receive status register and the transmitter status register. these error conditions are only valid for each word boundary and are not latched. when executing block tranfers or data, it is necessary to save any errors so that they can be checked at the end of a block. in order to save error conditions during data transfer, the MK68901 mfp interrupt controller may be used by enabling error in- terrupt for the desired channel (receive error or transmit error) and by masking these bits off. once the tranfer is complete, the interrupt pending regis- ter can be polled, to determine the precence of a pending error interrupt, and therefore an error. v000366 MK68901 18/33
unused bits in the sync character register are ze- roed out ; therefore, word length should be set up prior to writing the sync word in some cases. sync word length is the word length plus one when parity is enabled. the user has to determine the parity of the sync word when the word length is not 8 bits. the MK68901 mfp does not add a parity bit to the sync word if the word length is less than 8 bits. the extra bit in the sync word is transmitted as the parity bit. with a word length of eight, and parity selected, the parity bit for the sync word is computed an added on by the MK68901 mfp. rr receiver ready rr is asserted when the buffer full bit is set in the rsr unless a parity error or frame error is detected by the receiver. tr transmitter ready tr is asserted when the buffer empty bit is set in the tsr unless a break is currently being transmitted. register accesses all register accesses are dependent on clk as shown in the timing diagrams. to read a register, cs and ds must be asserted, and r/ w must by high. the internal read control signal is essentially the combi- nation of cs, ds, and rd/ wr. thus, the read ope- ration will begin when cs and ds go active and will end when either cs or ds goes inactive. the address bus must be stable prior to the start of the operation and must remain stable until the end of the operation. unless a read operation or interrupt acknowledge cy- cle is in progress the data bus (d 0 -d 7 ) will remain in the tri-state condition. to write a register, cs and ds must be asserted and r/ w must be low. the address must be stable prior to the start of the operation and must remain stable until the end of the operation. after the MK68901 as- serts dtack, the cpu negates ds,. at this time, the mfp latches the data bus and writes the contents in- to the appropriate register. also when ds is nega- ted, the mfp rescinds dtack. for an interrupt acknowledge, the operation starts when iack goes low, and ends when iack goes high. the data bus is tri-stated when either iack or ds goes high. when cs or iack are asserted the mfp starts an internal cycle. ds is needed to enable the address and data buffers. it is recommended taht cs and iack be gated by ds so that ds is always present whenever an mfp bus cycle starts. MK68901 19/33
d.c. characteristics t a =0 cto70 c;v cc =+5v 5% unless otherwise specified symbol parameter test condition min. max. unit v ih input high voltage 2.0 v cc +.3 v v il input low voltage 0.3 0.8 v v oh output high voltage (except dtack )i oh = 120 m a 2.4 v v ol output low voltage (except dtack )i ol = 2.0ma 0.5 v i ll power supply current outputs open 180 ma i li input leakage current v in = 0 to v cc 10 m a i loh tri-state output leakage current in float v out = 2.4 to v cc 10 m a i lol tri-state output leakage current in float v out = 0.5v 10 m a i oh dtack output source current v out = 2.4 400 m a i ol dtack output sink current v out = 0.5 5.3 ma all voltages are referenced to ground. capacitance t a =25 c, f = 1mhz unmeasured pins returned to ground. symbol parameter test condition max. unit c in input capacitance unmeasured pins returned to ground 10 pf c out tri-state output capacitance 10 pf MK68901 electrical specifications C preliminary absolute maximum ratings symbol parameter value unit t a temperature under bias 25 to + 100 c t stg storage temperature 65 to + 150 c v i voltage on any pin with respect to ground 0.3 to + 7 v p d power dissipation 1.5 w stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sec - tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect re- liability. MK68901 20/33
ac electrical characteristics (v cc = 5.0vdc 5%, gnd = 0vdc, t a =0 cto70 c) value MK68901-4 MK68901-5 number characteristic min. max. min. max. unit fig. note 1cs ,ds width high 50 35 ns 21,22 5 2r/w , a1-a5 valid to falling cs (setup) 0 0 ns 21,22 3 data valid prior to falling clk 280 0 ns 22 4cs , iack valid to falling clock (setup) 50 45 ns 21-24 3 5 clk low to dtack low 220 180 ns 21,22 6cs ,ds or iack high to dtack high 60 55 ns 21-24 7cs ,ds or iack high to dtack tri-state 100 95 ns 21-24 8 dtack low to data invalid (hold time) 0 0 ns 22 9cs ,ds or iack high to data tri-state 50 50 ns 21,23,24 10 cs or ds high to r/w , a1-a5 invalid (hold time) 0 0 ns 21,22 11 data valid from cs low 310 260 ns 21 3,6 12 read data valid to dtack low (setup) 50 50 ns 21 13 dtack low to ds ,cs or iack high (hold time) 0 0 ns 21-23 14 iei low to falling clk (setup) 50 50 ns 23,24 15 ieo valid from clock low (delay) 180 180 ns 23 1 16 data valid from clock low (delay) 300 300 ns 23 17 ieo invalid from iack high (delay) 150 150 ns 23, 24 18 dtack low from clock high (delay) 180 165 ns 23, 24 19 ieo valid from iei low (delay) 100 100 ns 24 1 20 data valid from iei low (delay) 220 220 ns 24 21 clock cycle time 250 1000 200 1000 ns 21 22 clock width low 110 90 ns 21 23 clock width high 110 90 ns 21 24 cs , iack inactive to rising clock (setup) 100 80 ns 21-23 4,5 25 i/o minimum active pulse width 100 100 ns 25 26 iack width high 2 2 t clk 23-24 2 27 i/o data valid from rising cs or ds 450 450 ns 26 28 receiver ready delay from rising rc 600 600 ns 27 29 transmitter ready delay from rising tc 600 600 ns 28 30 timer output low from rising edge of cs or ds (a & b) (reset t out ) 450 450 ns 29 7 31 t out valid from internal timeout 2 t clk + 300 2t clk + 300 ns 29 2 32 timer clock low time 110 90 ns 29 MK68901 21/33
ac electrical characteristics (continued) (v cc = 5.0vdc 5%, gnd = 0vdc, t a =0 cto70 c) value MK68901-4 MK68901-5 number characteristic min. max. min. max. unit fig. note 33 timer clock high time 110 90 ns 29 34 timer clock cycle time 250 1000 200 1000 ns 29 35 reset low time 2 1.8 m s30 36 delay to falling intr from external interrupt active transition 380 380 ns 25 37 transmitter internal interrupt delay from falling edge of tc 550 550 ns 28 38 receiver buffer full interrupt transition delay from rising edge of rc 800 800 ns 27 39 receiver error interrupt transition delay from falling edge of rc 800 800 ns 27 40 serial in set up time to rising edge of rc (divide by one only) 80 70 ns 27 41 data hold time from rising edge of rc (divide by one only) 350 325 ns 27 42 serial output data valid from falling edge of tc ( ? 1) 440 420 ns 28 43 transmitter clock low time 500 450 ns 28 44 transmitter clock high time 500 450 ns 28 45 transmitter clock cycle time 1.05 0.95 m s28 46 receiver clock low time 500 450 ns 27 47 receiver clock high time 500 450 ns 27 48 receiver clock cycle time 1.05 0.95 m s27 49 cs , iack ,ds width low 80 80 t clk 29 2 50 serial output data valid from falling edge of tc ( ? 16) 490 370 ns 28 notes : 1. ieo only goes low if no acknowledgeable interrupt is pending. if ieo goes low, dtack and the data bus re- main tri-stated. 2. t clk refers to the clock applied to the mfp clk input pin. t clk refers to the timer clock signal, regardless of whether that signal comes from the xtal 1/xtal2 crys- tal clock inputs or the tai or tbi timer inputs. 3. if the setup time is not met, cs or iack will not be reco- gnized until the next falling clk. 4. if this setup time is met (for consecutive cycles), the mi- nimum hold-off time of one clock cycle will be obtained. if not met, the hold-off will be two clock cycles. 5. cs is latched internally, therefore if spec's 1 and 24 are met then cs may be reasserted before the rising clock and still terminate the current bus cycle. the new bus cy- cle will be delayed by the MK68901 until all appropriate internal operations have completed. 6. although cs and dtack are synchronized with the clock, the data out during a read cycle is asynchronous to the clock, relying only on cs for timing. 7. spec. 30 applies to timer outputs tao and tbo only. MK68901 22/33
timer a.c. characteristics definitions : error = indicated time value - actual time value tpsc = t clk x prescale value internal timer mode single interval error (free running) (note 2) 100ns cumulative internal error 0 error between two timer reads (tpsc + 4t clk ) start timer to stop timer error + (2t clk + 100ns) to - (tpsc + 6t clk + 100ns) start timer to read timer error + 0 to (tpsc + 6t clk + 400ns) start timer to interrupt request error (note 3) - 2t clk to (4t clk + 800ns) notes : 1. error may be cumulative if repetitively performed. 2. error with respect to t out or int if note 3 is true. 3. assuming it is possible for the timer to make an interrupt request immediately. pulse width measurement mode measurement accuracy (note 1) + 2t clk to (tpsc + 4t clk ) minimum pulse width 4t clk event counter mode minimum active time of tai, tbi 4t clk minimum inactive time of tai, tbi 4t clk MK68901 23/33
figure 21 : read cycle. figure 22 : write cycle. note : cs and iack must be a function of ds. v000367 v000368 MK68901 24/33
figure 23 : interrupt acknowledge ( iei low). figure 24 : interrupt acknowledge cycle ( iei high). note : cs and iack must be a function of ds. v000370 v000369 MK68901 25/33
figure 25 : interrupt timing. figure 26 : port timing. note : active edge is assumed to be the rising edge. v000371 v000372 MK68901 26/33
figure 27 : receiver timing. figure 28 : transmitter timing. v000347 v000346 MK68901 27/33
figure 29 : timer timing. figure 30 : reset timing. v000348 v000349 MK68901 28/33
figure 31 : typical output. figure 32 : intr test load. for all outputs except dtack c l = 100pf r l = 20k w r 1 = 180 w for dtack c l = 130pf r l = 6k w r 1 = 470 w figure 33 : MK68901 mfp external oscillator components. crystal parameters : parallel resonance, fundamental mode at cut r s 150 w (f r = 2.8 C 5.0mhz); r s 300 w (f r = 2.0 C 2.7mhz) c l = 18pf ; c m = 0.02pf ; c h = 5pf ; l m = 96mh f r (typ) = 2.4576mhz MK68901 order codes part number package type max. clockfrequency temperaturerange 68901p04 68901p05 68901n04 68901n05 68901q04 68901q05 ceramic dip ceramic dip plastic dip plastic dip plastic plcc plastic plcc 4.0mhz 5.0mhz 4.0mhz 5.0mhz 4.0mhz 5.0mhz 0 to 70 c 0 to 70 c 0 to 70 c 0 to 70 c 0 to 70 c 0 to 70 c v000333 v000373 v000374 MK68901 29/33
MK68901 48Cpin plastic dualCinCline package (n) millimeters inches dim min. max. min. max. a 61.468 62.738 2.420 2.470 b 14.986 16.256 .590 .640 c 13.462 13.97 .530 .550 d 3.556 4064 .140 .160 e 0.381 1.524 .015 .060 f 3048 3.81 .120 .150 g 1.524 2.286 .060 .090 h 1.186 1.794 .090 .110 j 15.24 17.78 .600 .700 k 0.381 0.533 .015 .021 l 0.203 0.305 .008 .012 m 1.143 1.778 .045 .070 MK68901 30/33
MK68901 48Cpin ceramic dualCinCline package (p) inches dim min. max. a 2.376 2.424 b 0.576 0.604 c 0.120 0.160 d 0.015 0.021 f 0.030 0.055 g 0.100 bsc j 0.008 0.013 k 0.100 0.165 l 0.590 0.616 m0 10 n 0.040 0.060 MK68901 31/33
MK68901 52Cpin plastic leaded chip carrier (q) inches dim min. max. a .165 .180 a 1 .090 .130 d .785 .795 d 1 .750 .756 d 2 .690 .730 e .785 .795 e 1 .750 .756 e 2 .690 .730 h .042 .048 j .042 .048 k .013 .024 l .008 .014 m .026 .032 n/n 1 .043 .048 MK68901 32/33
MK68901 pin connections plcc dip func. plcc dip func. plcc dip func. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc r/w a1 a2 a3 a4 a5 tc so si rc v cc nc nc tao tbo tco tdo 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 xtal1 xtal2 nc tai tbi reset io i1 i2 i3 i4 i5 i6 i7 nc tr rr intr 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ieo iei clk gnd d0 d1 d2 d3 d4 d5 d6 d7 iack dtack ds cs note : nc C no connection information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. MK68901 33/33

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